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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 1 1 publication order number: NCP81381/d NCP81381 integrated driver and mosfet the NCP81381 integrates a mosfet driver, high?side mosfet and low?side mosfet into a single package. the driver and mosfets have been optimized for high?current dc?dc buck power conversion applications. the NCP81381 integrated solution greatly reduces package parasitics and board space compared to a discrete component solution. features ? capable of average currents up to 25 a ? capable of switching at frequencies up to 2 mhz ? capable of peak currents up to 60 a ? compatible with 3.3 v or 5 v pwm input ? responds properly to 3?level pwm inputs ? option for zero cross detection with 3?level pwm ? zcd_en input for diode emulation with 2?level pwm ? internal bootstrap diode ? undervoltage lockout ? supports intel ? power state 4 ? thermal warning output ? thermal shutdown ? this is a pb?free device applications ? desktop & notebook microprocessors figure 1. application schematic 5 v smod from controller pwm from controller drvon from controller detect enable zero current zcd_en disb# pwm smod# vcc thwn boot vsw vccd vin cgnd pgnd vout vin phasef phased zcd_en vccd vcc 36 6 19 5 20 4 21 3 22 2 23 1 24 7 35 8 34 9 33 10 32 11 31 12 30 13 29 14 28 15 27 16 26 17 25 18 boot gl phased gl gh gl phasef gl pgnd vsw vin vsw vin vsw vin vsw vin vsw vin vsw vin vsw pgnd cgnd pgnd pwm pgnd smod# pgnd disb# pgnd thwn pgnd pgnd test 38 37 www. onsemi.com device package shipping ? ordering information NCP81381mntxg qfn36 (pb?free) 2500 / tape & reel (top view) pinout diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 136 a = assembly location l = wafer lot y = year w = work week = pb?free package 81381 alyw (note: microdot may be in either location) qfn36 6x4 case 485dz marking diagram
NCP81381 www. onsemi.com 2 figure 2. block diagram vccd 7 vcc 6 pwm 4 smod# 3 disb# 2 zcd_en 36 phased 34 level vcc shift vcc control pgnd 37 level shift dead time sense uvlo control logic zcd boot 35 gh 33 pgnd 31 cgnd 5 thwn 1 shutdown warning temp phasef 32 pgnd 20 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 19 25 ? 30 vin 12 ? 18 vsw gl 8 gl 9 gl 10 gl 11 test 38 pin list and descriptions pin no. symbol description 1 thwn thermal warning indicator. this is an open?drain output. when the temperature at the driver die reaches t thwn , this pin is pulled low. 2 disb# output disable pin. when this pin is pulled to a logic high level, the driver is enabled. there is an internal pull?down resistor on this pin. 3 smod# skip mode pin. 3?state input (see table 1 logic table ): smod# = high states of zcd_en and pwm determine whether the NCP81381 performs zcd or not. smod# = mid connects pwm to internal resistor divider placing a bias voltage on pwm pin. otherwise, logic is equivalent to smod# in the high state. smod# = low placing pwm into mid?state pulls gh and gl low without delay. there is an internal pull?up resistor to vcc on this pin. 4 pwm pwm control input and zero current detection enable 5 cgnd signal ground 6 vcc control power supply input 7 vccd driver power supply i nput 8 gl low side fet gate access 9 gl low side fet gate access 10 gl low side fet gate access 11 gl low side fet gate access 12 vsw switch node output 13 vsw switch node output 14 vsw switch node output 15 vsw switch node output 16 vsw switch node output 17 vsw switch node output 18 vsw switch node output
NCP81381 www. onsemi.com 3 pin list and descriptions (continued) pin no. description symbol 19 pgnd power ground 20 pgnd power ground 21 pgnd power ground 22 pgnd power ground 23 pgnd power ground 24 pgnd power ground 25 vin conversion supply power input 26 vin conversion supply power input 27 vin conversion supply power input 28 vin conversion supply power input 29 vin conversion supply power input 30 vin conversion supply power input 31 pgnd power ground 32 phasef bootstrap capacitor return (must be connected to phased) 33 gh high side fet gate access 34 phased driver phase connection (must be connected to phasef) 35 boot bootstrap voltage 36 zcd_en pwm drive logic and zero current detection enable. 3?state input: pwm = high gh is high, gl is low. pwm = mid diode emulation mode. pwm = low gh is low. state of gl is dependent on states of smod# and zcd_en (see table 1 logic table ). 37 pgnd power ground 38 test no connection should be made to this pin. no pad is needed on the pcb footprint absolute maximum ratings (electrical information ? all signals referenced to pgnd unless noted otherwise) (note 1) pin name min max unit vcc, vccd ?0.3 6.5 v gh to phased (dc) ?0.3 v boot ? v sw + 0.3 v gh to phased (< 50 ns) ?5 7.7 v vin ?0.3 30 v boot (dc) ?0.3 35 v boot (< 20 ns) ?0.3 40 v boot to phased (dc) ?0.3 6.5 v vsw, phased, phasef (dc) ?0.3 30 v vsw, phased, phasef (< 5 ns) ?5 37 v all other pins ?0.3 v vcc + 0.3 v single?pulse drain?to?source avalanche energy, high?side fet (t j = 25 c, v gs = 5 v, l = 0.1 mh, r g = 25 , i l = 54 a pk ) 144 mj single?pulse drain?to?source a valanche energy, low?side fet (t j = 25 c, v gs = 5 v, l = 0.3 mh, r g = 25 , i l = 31.5 a pk ) 180 mj single?pulse drain?to?source avalanche energy, high?side fet (t j = 25 c, l = 0.15 h, i l = 90 a pk , v ds dv/dt= 30 v / 2 ns) 200 j single?pulse drain?to?source a valanche energy, low?side fet (t j = 25 c, l = 150 nh, i l = 90 a pk , v ds dv/dt= 30 v / 4 ns) 200 j stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. absolute maximum ratings are not tested in production.
NCP81381 www. onsemi.com 4 thermal information rating symbol value unit thermal resistance ja 22 c/w r j?bt 2.0 c/w r j?ct 4.0 c/w operating junction temperature range (note 2) t j ?40 to +150 c operating ambient temperature range ?10 to +100 c maximum storage temperature range t stg ?40 to +150 c maximum power dissipation 5.0 w moisture sensitivity level msl 3 2. the maximum package power dissipation must be observed. 3. jesd 51?5 (1s2p direct?attach method) with 0 lfm 4. jesd 51?7 (1s2p direct?attach method) with 0 lfm recommended operating conditions parameter pin name conditions min typ max unit supply voltage range vcc, vccd 4.5 5.0 5.5 v conversion voltage vin 4.5 12 20 v continuous output current f sw = 1 mhz, v in = 12 v, v out = 1.1 v 20 a f sw = 500 khz, v in = 12 v, v out = 1.1 v 25 a peak output current f sw = 500 khz, v in = 12 v, v out = 1.1 v, duration = 10 ms, period = 1 s 60 a operating temperature ?10 100 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. electrical characteristics (v vcc =v vccd = 5.0 v, v vin =12v, v disb# = 2.0 v, c vccd =c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit vcc supply current operating disb# = 5 v, zcd_en = 5 v, pwm = 400 khz ? 1 2 ma no switching, zcd enabled disb# = 5 v, zcd_en = 5 v, pwm = 0 v ? ? 2 ma no switching, zcd disabled disb# = 5 v, zcd_en = 0 v, pwm = 0 v ? ? 1.8 ma disabled disb# = 0 v zcd_en = vcc, smod# = vcc ? 0.1 1 a disb# = 0 v zcd_en = vcc, smod# = gnd 10 13 a disb# = 0 v zcd_en = smod# = gnd ? 27 40 a uvlo start threshold v uvlo vcc rising 2.9 ? 3.3 v uvlo hysteresis 150 ? ? mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCP81381 www. onsemi.com 5 electrical characteristics (continued) (v vcc =v vccd = 5.0 v, v vin =12v, v disb# = 2.0 v, c vccd =c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol vccd supply current operating disb# = 5 v, zcd_en = 5 v, pwm = 400 khz ? ? 15 ma enabled, no switching disb# = 5 v, pwm = 0 v, v phased = 0 v ? 175 300 a disabled disb# = 0 v ? 0.1 1 a disb# input input resistance to ground, @ 25 c ? 461 ? k upper threshold v upper ? ? 2.0 v lower threshold v lower 0.8 ? ? v hysteresis v upper ? v lower 200 ? ? mv enable delay time t enable time from disb# transitioning hi to when vsw responds to pwm. ? ? 40 s disable delay time t disable time from disb# transitioning low to when both output fets are off. ? 25 50 ns pwm input input high voltage v pwm_hi 2.65 ? ? v input mid?state voltage v pwm_mid 1.4 ? 2.0 v input low voltage v pwm_lo ? ? 0.7 v input resistance r pwm _ hiz smod# = v smod#_hi or v smod#_lo 10 ? ? m input resistance r pwm_bias smod# = v smod#_mid ? 63 ? k pwm input bias voltage v pwm_bias smod# = v smod#_mid ? 1.7 ? v pwm propagation delay, rising tpdl gl pwm = 2.25 v to gl = 90%; smod# = low ? 25 35 ns pwm propagation delay, falling tpdl gh pwm = 0.75 v to gh = 90% ? 15 25 ns exiting pwm mid?state propagation delay, mid?to?low t pwm_exit_l pwm = mid?to?low to gl = 10%, zcd_en = high ? 13 25 ns exiting pwm mid?state propagation delay, mid?to?high t pwm_exit_h pwm = mid?to?high to gh = 10% ? 13 25 ns smod# input smod# input voltage high v smod_hi 2.65 ? ? v smod# input voltage mid?state v smod#_mid 1.4 ? 2.0 v smod# input voltage low v smod_lo ? ? 0.7 v smod# input resistance r smod#_up pull?up resistance to vcc ? 440 ? k smod# propagation delay, falling t smod#_pd_f smod# = low to gl = 90%, pwm = low ? 26 30 ns smod# propagation delay, rising t smod#_pd_r smod# = high to gl = 10%, zcd_en = high, pwm = low ? 15 30 ns zcd_en input zcd_en input voltage high v zcd_en_hi 2.0 ? ? v zcd_en input voltage low v zcd_en_lo ? ? 0.8 v zcd_en hysteresis v zcd_en_hys ? 250 ? mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCP81381 www. onsemi.com 6 electrical characteristics (continued) (v vcc =v vccd = 5.0 v, v vin =12v, v disb# = 2.0 v, c vccd =c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ?10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol zcd_en input zcd_en input resistance r zcd_en_pu to vcc ? 270 ? k zcd_en propagation delay, rising t zcd_en,pd_r smod# = high, zcd_en = high to gl = 10% ? 40 45 ns zcd_en propagation delay, falling t zcd_en,pd_f smod# = high, zcd_en = low to gl = 90% ? 25 40 ns zcd function zero cross detect threshold v zcd ? ?6.5 ? mv zcd blanking + debounce time t blnk ? 330 ? ns non?overlap delays non?overlap delay, leading edge tpdh gh gl falling = 1 v to gh?vsw rising = 1 v ? 13 ? ns non?overlap delay, trailing edge tpdh gl gh?vsw falling = 1 v to gl rising = 1 v ? 12 ? ns thermal warning & shutdown thermal warning temperature t thwn temperature at driver die ? 150 ? c thermal warning hysteresis t thwn_hys ? 15 ? c thermal shutdown temperature t thdn temperature at driver die ? 180 ? c thermal shutdown hysteresis t thdn_hys ? 25 ? c thwn open drain current i thwn ? ? 5 ma booststrap diode forward voltage forward bias current = 2.0 ma ? 300 ? mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. disb# pwm gh?vsw vsw gl enable tpdl tpdh tpdl tpdh t gl gl disable gh gh t 1v 1v 90% 90% 1v 1v 10% figure 3. timing diagram
NCP81381 www. onsemi.com 7 table 1. logic table input truth table disb# pwm smod# (note 5) zcd_en gh gl l x x x l l h h x x h l h l x l l l h l x h l h h mid h or mid h l zcd (note 6) h mid x l l l (note 7) h mid l x l l (note 7) 5. pwm input is driven to mid?state with internal divider resistors when smod# is driven to mid?state and pwm input is undriven externally. 6. gl goes low following 80 ns de?bounce time, 250 ns blanking time and then sw exceeding zcd threshold. 7. there is no delay before gl goes low. figure 4. efficiency ? 12 v input, 1.2 v output, 500 khz figure 5. efficiency ? 19 v input, 1.2 v output, 500 khz
NCP81381 www. onsemi.com 8 applications information theory of operation the NCP81381 is an integrated driver and mosfet module designed for use in a synchronous buck converter topology. the NCP81381 supports numerous application control definitions including zcd (zero current detect) with pin enable and alternately pwm tristate control. a pwm input signal is required to control the drive signals to the high?side and low?side integrated mosfets. low?side driver the low?side driver drives an internal, ground?referenced low?r ds (on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vccd and pgnd pins. high?side driver the high?side driver drives an internal, floating low?r ds (on) n?channel mosfet. the gate voltage for the high side driver is developed by a bootstrap circuit referenced to switch node (vsw, phasef and phased) pins. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor and resistor. when the NCP81381 is starting up, the vsw pin is at ground, allowing the bootstrap capacitor to charge up to vccd through the bootstrap diode (see figure 1). when the pwm input is driven high, the high?side driver will turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the voltage at the vsw, phasef and phased pins rise. when the high?side mosfet is turned fully on, the switch node will settle to vin and the bst pin will settle to vin + vccd (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the hs driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used as the bootstrap capacitor. an 4 resistor in series with c bst is recommended to decrease vsw overshoot. power supply decoupling the NCP81381 will source relatively large currents into the mosfet gates. in order to maintain a constant and stable supply voltage (vccd) a low?esr capacitor should be placed near the power and ground pins. a multi layer ceramic capacitor (mlcc) between 1 f and 4.7 f is typically used. a separate supply pin (vcc) is used to power the analog and digital circuits within the driver. a 1 f ceramic capacitor should be placed on this pin in close proximity to the NCP81381. it is good practice to separate the vcc and vccd decoupling capacitors with a resistor (10 typical) to avoid coupling driver noise to the analog and digital circuits that control driver function (see figure 1). safety timer and overlap protection circuit it is important to avoid cross?conduction of the two mosfets which could result in a decrease in the power conversion efficiency or damage to the device. the NCP81381 prevents cross conduction by monitoring the status of the mosfet gates and applying the appropriate amount of non?overlap time (the time between the turn?off of one mosfet and the turn?on of the other mosfet). when the pwm input pin is driven high, the low?side mosfet gate (gl) starts to go low after a propagation delay (tpdl gl ). the time it takes for the low?side mosfet to turn off is dependent on the low?side mosfet gate charge. the high?side mosfet gate begins to rise a fixed time (tpdh gh ) after the gl voltage falls below the low?side mosfet gate threshold. when the pwm input pin is driven low, the high?side mosfet gate (gh) starts to go low after a propagation delay (tpdl gh ). the time it takes for the high?side mosfet to turn off is dependent on the high?side mosfet gate charge. the low?side mosfet gate begins to rise a fixed time (tpdh gh ) after the gh voltage falls below the high?side mosfet gate threshold. zero current detect enable input (zcd_en) the zcd_en pin is a logic input pin with an internal pull?up resistance to vcc. when zcd_en is set low, the NCP81381 will operate in synchronous rectifier (pwm) mode. this means that negative current can flow in the ls mosfet if the load current is less than ? delta current in the inductor. when zcd_en is set high, zero current detect pwm (zcd_pwm) mode will be enabled with zcd_en set high, when pwm rises above v pwm_hi , gl will go low and gh will go high after the non?overlap delay. subsequently, if pwm falls to less than v pwm_hi , but stays above v pwm_lo , gl will go high after the non?overlap delay, and stay high for the duration of the zcd blanking + debounce time (t blnk ). once this timer has elapsed, vsw will be monitored for zero current, and gl will be pulled low when zero current is detected. the vsw zero current th reshold u ndergoes an auto?calibration cycle every time disb# is brought from low to high. pwm input the pwm input pin is a tri?state input used to control the hs mosfet on/off state. in conjunction with zcd_en it also determines the state of the ls mosfet. see table1 for logic operation. the pwm in some cases must operate with frequency programming resistances to ground. these resistances can range from 10 k to 300 k depending on the application. when smod# is set to > vsmod#_hi or to < vsmod#_lo, the input impedance to the pwm input is very high in order to avoid interferences with controllers that must use programming resistances on the pwm pin.
NCP81381 www. onsemi.com 9 if v smod#_lo < smod# < v smod#_hi (mid?state), internal resistances will set undriven pwm pin voltage to mid?state. disable input (disb#) the disb# pin is used to disable the gh to the high?side fet to prevent power transfer. the pin has a pull?down resistance to force a disabled state when it is left unconnected. disb# can be driven from the output of a logic device or set high with a pull?up resistance to vcc. vcc undervoltage lockout the vcc pin is monitored by an undervoltage lockout circuit (uvlo). vcc voltage above the rising threshold enables the NCP81381. table 2. uvlo/disb# logic table uvlo disb# driver state l x disabled (gh = gl = 0) h l disabled (gh = gl = 0) h h enabled (see table x) h open disabled (gh = gl = 0) thermal warning/thermal shutdown output the thwn pin is an open drain output. when the temperature of the driver exceeds t thwn , the thwn pin will be pulled low indicating a thermal warning. at this point, the part continues to function normally. when the temperature drops t thwn_hys below t thwn , the thwn pin will go high. if the driver temperature exceeds t thdn , the part will enter thermal shutdown and turn off both mosfets. once the temperature falls t thdn_hys below t thdn , the part will resume normal operation. skip mode input (smod#) the smod# tri?state input pin has an internal pull?up resistance to vcc. when driven high, the smod# pin enables the low side synchronous mosfet to operate independently of the internal zcd function. when the smod# pin is set low during the pwm cycle it disables the low side mosfet to allow discontinuous mode operation. the NCP81381 has the capability of internally connecting a resistor divider to the pwm pin. to engage this mode, smod# needs to be placed into mid?state. while in smod# mid?state, the ic logic is equivalent to smod# being in the high state. figure 6. pwm timing diagram zcd_en pwm gh gl inductor current 250 ns 80 ns de-bounce timer zcd blanking timer zcd detected 250 ns 80 ns zcd blanking timer zcd waits until timers expire zcd_en pwm gh gl inductor current de-bounce timer notes: if the zero current detect circuit detects zero current after the zcd wait timer period, the gl is driven low by the zero current detect signal. if the zero current detect circuit detects zero current before the zcd wait timer period has expired, the zero current detect signal is ignored and the gl is driven low at the end of the zcd wait timer period.
NCP81381 www. onsemi.com 10 figure 7. smod# timing diagram gh pwm inductor current smod# triggered gl smod# note: if the smod# input is driven low at any time after the gl has been driven high, the smod# falling edge will trigger the gl to go low. if the smod# input is driven low while the gh is high, the smod# input is ignored . figure 8. zcd_en timing diagram t zcd_blank + t debounce gl gh pwm zcd_en smod# zcd triggered inductor current 0 a ls fet on until zcd ls fet is off smod# = high note: when zcd is enabled by pulling zcd_en# high, the NCP81381 keeps the ls fet on until it detects zero current, reducing power loss.
NCP81381 www. onsemi.com 11 for use with controllers with 3?state pwm and no zero current detection capability: table 3. logic table ? 3?st ate pwm controllers with no zcd pwm smod# zcd_en gh gl h h h on off m h h off zcd l h h off on this section describes operation with controllers that are capable of 3 states in their pwm output and relies on the NCP81381 to conduct zero current detection during discontinuous conduction mode (dcm). the smod# pin needs to either be set to 5 v or left disconnected. the NCP81381 has an internal pull?up resistor that connects to vcc that sets smod# to the logic high state if this pin is disconnected. the zcd_en pin needs to either be set to 5 v or left disconnected. the NCP81381 has an internal pull?up resistor connected to vcc that will set zcd_en to the logic high state if this pin is left disconnected. to operate the buck converter in continuous conduction mode (ccm), pwm needs to switch between the logic high and low states. to enter into dcm, pwm needs to be switched to the mid?state. whenever pwm transitions to mid?state, gh turns off and gl turns on. gl stays on for the duration of the de?bounce timer and zcd blanking timers. once these timers expire, the NCP81381 monitors the sw voltage and turns gl off when sw exceeds the zcd threshold voltage. by turning off the ls fet, the body diode of the ls fet allows any positive current to go to zero but prevents negative current from conducting. figure 9. timing diagram ? 3?state pwm controller, no zcd
NCP81381 www. onsemi.com 12 for use with controllers with 3?state pwm and zero current detection capability: table 4. logic table ? 3?state pwm controllers with zcd pwm smod# zcd_en gh gl h l h on off m l h off off l l h off on this section describes operation with controllers that are capable of 3 pwm output levels and have zero current detection during discontinuous conduction mode (dcm). the smod# pin needs to be pulled low (below v smod#_lo ). the zcd_en pin needs to either be set to 5 v or left disconnected. there is an internal pull?up resistor that connects to vcc and sets zcd_en to the logic high state if this pin is left disconnected. to operate the buck converter in continuous conduction mode (ccm), pwm needs to switch between the logic high and low states. during dcm, the controller is responsible for detecting when zero current has occurred, and then notifying the NCP81381 to turn off the ls fet. when the controller detects zero current, it needs to set pwm to mid?state, which causes the NCP81381 to pull both gh and gl to their off states without delay. figure 10. timing diagram ? 3?state pwm controller, with zcd gl gh pwm zcd_en 5 v smod# 0 v smod# = low pwm in mid?state pulls gl low. controller detects zero current sets pwm to mid?state. zcd_en = high il 0 a
NCP81381 www. onsemi.com 13 for use with controllers with 2?level pwm and zero current detection capability: table 5. logic table ? 2?state pwm controllers with zcd pwm smod# zcd_en gh gl h l x on off l l h off on l l l off off this section describes operation with controllers that do not have 3?level pwm output capability but are capable of zero current detection during discontinuous conduction mode (dcm). the smod# pin needs to be pulled low (below v smod#_lo ). when pwm is high, gh will always be in the high state and gl will always be in the low state, regardless of the state zcd_en is in. when pwm is in the low state, the state of zcd_en determines whether the converter is placed into diode emulation mode. when the controller detects positive inductor current, zcd_en should be in the high state, allowing the ls fet to be on and conducting. once the controller detects zero or negative current, zcd_en should be placed into the low state, turning off the ls fet. with the ls fet turned off, the body diode of the ls fet allows any positive current that may still be flowing to reach zero, but prevents the current from flowing in the negative direction. figure 11. timing diagram ? 2?state pwm controller, with zcd gl gh pwm zcd_en il 0 a smod# 0 v smod# = low low zcd_en pulls gl low. controller detects zero current sets zcd_en low.
NCP81381 www. onsemi.com 14 recommended pcb layout (viewed from top) input bypass caps output bypass caps output bypass cap output bypass caps output bypass cap inductor NCP81381 snubber bootstrap rc input bypass caps vcc bypass cap vin gnd vsw vout gnd input bypass caps vccd bypass cap gnd vout vin testpoint figure 12. top copper layer figure 13. bottom copper layer figure 14. layer 2 copper layer (ground plane)
NCP81381 www. onsemi.com 15 package dimensions qfn36 6x4, 0.4p case 485dz issue a dim min max millimeters a 0.90 1.20 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.95 5.05 e 4.00 bsc e2 2.44 2.54 e 0.40 bsc g 0.52 0.62 0.15 c d e b a 2x 2x note 4 a a1 (a3) 0.15 c pin one reference 0.08 c 0.10 c c seating plane side view top view *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* g1 0.43 0.53 recommended d3 0.91 1.01 d4 3.04 3.14 d5 2.70 2.80 e3 1.14 1.24 e4 2.29 2.39 h 1.35 1.45 h1 0.60 0.70 h2 0.57 0.68 l 0.30 0.50 l2 0.15 0.35 d2 e2 bottom view b e 36x l 30x e3 note 3 7 18 24 36 e/2 a m 0.10 b c m 0.05 c 1 d5 d4 d3 e4 bottom view supplemental l2 6x h1 h g g1 h2 detail a 2x no exposed 0.66 1.45 0.78 1.23 r0.15 0.40 pitch all sides 3.26 1.13 detail a 0.63 1.25 0.60 30x 1 0.30 6x 4.30 1.37 1.29 0.25 36x 2.37 2.85 0.78 metal allowed
NCP81381 www. onsemi.com 16 package dimensions qfn36 6x4, 0.4p case 485dz recommended solder stencil on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81381/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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